1. Field of the Invention
The present invention relates to the conversion of circuit board information used for supporting the thermal design of circuit boards, and particularly to a technique of improving the accuracy of thermal analysis.
2. Description of the Related Art
In recent years, simulations and the production of prototypes have been repeatedly performed for calculating the thermal influence of heat sources because heat sources on circuit boards have a great influence on the thermal design of the entire circuit board in circuit board (such as multilayer printed circuit boards that are mounting boards on which LSI package boards are mounted, and the like) design. Thus, various types of simulation systems and programs for supporting the thermal design of circuit boards have been developed.
In thermal design, detailing heat dissipation paths is important in order to improve the accuracy of the thermal analysis (using the finite volume method or the like) of circuit boards. In particular, under the condition of the self-cooled configuration, heat dissipation occurs mainly to the side of circuit boards; accordingly, modeling in which wiring on boards, via holes and the like are taken into consideration is required.
As one of several conventional techniques, information on layer configuration, wire traces, shapes of via holes, and the like is used for the modeling on the basis of intermediate files (IGES, or Initial Graphics Exchange Specification) of output data from CAD (Computer Aided Design) tools and STEP (Standard for the Exchange of Product model data).
However, when the modeling is performed in detail, by using the conventional thermal analysis models as above, on the basis of circuit board design information such as the layer configuration, the wire traces, and the shapes of via holes, the scale of the analysis model becomes great, and a longer time is required for the calculation.
In order to reduce the scale of analysis, simplified modeling is performed by defining equivalent thermal conductivity on the basis of the wiring percentage of copper (Cu), and by defining via holes or the like by the anisotropic thermal conductivity. However, although the scale of modeling is made smaller and the time required for the calculation is shortened, the analysis accuracy deteriorates because the heat dissipation paths are simplified if the definitions are based on the equivalent thermal conductivity and the anisotropic thermal conductivity.
According to Patent Document 1, when conducting heat designing, information included in the respective layers in a multilayer printed circuit board, such as wire traces, through holes, heat sources, resin and the like, is acquired by using a data file in the format of a two-dimensional CAD, and the operator makes the simulation model closer to the actual circuit board by selecting the information necessary for the thermal design simulation, such as the materials, dimensions and the like. Thereafter, the simulation model is created on the basis of the added information. This method suggests the creation of a simulation model that allows the accurate calculation of heat influence when a simulation is performed for the thermal design on multilayer printed circuit boards.
However, Patent Document 1 discloses the method in which the operator selects an appropriate setting for improving the accuracy of the thermal design simulation, but does not disclose the method of automatically simplifying simulation models, shortening the time required for calculation, or improving the accuracy of analysis.
According to Patent Document 2, antenna effects and errors such as errors against timing limitations are analyzed in an error analysis step on the layout data that includes redundant via holes, and it is determined whether or not there is an error, and the number of via holes from among the via holes on the signal wire that have a design limitation violation that are required to be reconfigured as single via holes in order to avoid the design limitation violation is calculated in the error determination step, and in the via hole conversion step, the erroneous redundant via holes are reconfigured as the single via holes on the basis of the calculation result. The suggestion has been made to arrange as many redundant via holes as possible while avoiding design limitation violations such as errors against the antenna effects, the timing limitations, and the like that are caused by the conversion from the single via holes into the redundant via holes in order to improve the yield.
However, Patent Document 2 discloses the technique of arranging via holes on the actual board, and does not disclose the technique of creating analysis models used for the thermal design. Accordingly, it is impossible to simplify the analysis models, to shorten the time for the analysis, or to improve the analysis accuracy on the basis of the technique disclosed in Patent Document 2.
Patent Document 1
Japanese Patent Application Publication No. 2005-216017
Patent Document 2
Japanese Patent Application Publication No. 2006-135152